The proliferation of mobile communication devices including mobile phones, personal digital assistants (PDAs) and laptops has resulted in significant efforts to provide efficient wireless transmission through adoption of new standards, hardware improvements and more sophisticated network management. As a result, there has been an ever increasing pressure to reduce cost, size and power consumption of such systems. This has driven designers to develop transceivers with higher levels of integration with much of the work focused on replacing the external components with integrated counterparts. This is not a trivial matter and often necessitates design of completely new transceiver architectures to achieve fewer off chip components.
On the other hand the quest for connectivity anytime and anywhere has created the need for more than one transceiver to be incorporated into a single device so that transmission can be achieved over multiple air interfaces and frequency bands. Hence, numerous solutions have been adopted to deploy multiplicity of transceivers using technologies such as multichip modules and multidie packages. Unfortunately, these approaches tend to introduce a significant amount of redundancy and reduced reliability, require more die area for each additional transceiver, and draw additional current leading to more power dissipation, large form factor and excessive bill of materials.
On this basis a fully integrated transceiver covering a heterogeneous set of mobile standards has been one of the major challenges facing the designers. The transceiver architectures used in the prior art can be categorized as one of the configurations of High IF (Superheterodyne), Zero-IF (Homodyne), Low-IF and combinations thereof. The Superheterodyne architecture is based on an Intermediate Frequency (IF) which lies between the baseband and RF transmit and receive frequencies. The IF frequency can be typically fixed anywhere between a few tens of kHz to hundreds of MHz, depending on the bandwidth and required RF frequency. In this architecture channel selection is achieved at a first IF requiring a local oscillator (LO) synthesizer with low phase noise performance. In addition, an external image filter is required at the IF for which integration is difficult to achieve due to the high specification and large filter component values. On the other hand Zero IF architecture eliminates the external filters by converting the signal directly from baseband to RF and vice versa. A key advantage of this architecture is that only a single synthesizer is required because the IF is eliminated, offering yet another saving in complexity and cost. The implementation, however, suffers from the well known problems caused by LO leakage and DC offset, limiting its application to certain modulation schemes and frequencies. The low-IF architecture has been developed to counteract such issues where IF is positioned at a given frequency. In this architecture, a bandpass filter is required for the channel selection which can be implemented in integrated form; however the poor image rejection due to the limited performance of the on chip components is one of the major drawbacks. The low-IF architecture also utilizes an LO synthesizer with low phase noise performance requirements, posing yet another design challenge.
On this basis, the current transceiver architectures are highly optimized and tuned for a given modulation scheme and frequency band. In order to cover multiple frequency bands and/or standards, several such transceivers need to be deployed which are typically implemented over several ICs.